[p LITE_MODE AUTOSTATIC IEEE_FLT IEEE_DBL LFSROK EMI_WORD ]
[d version 1.1 ]
[d edition pro ]
[d chip 18F25K50 ]
[d frameptr 4065 ]
"4 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\fleq.c
[v ___fleq __fleq `(b  1 e 0 0 ]
"62 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\float.c
[v ___ftpack __ftpack `(f  1 e 4 0 ]
"86 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\ftadd.c
[v ___ftadd __ftadd `(f  1 e 4 0 ]
"54 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\ftdiv.c
[v ___ftdiv __ftdiv `(f  1 e 4 0 ]
"62 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\ftmul.c
[v ___ftmul __ftmul `(f  1 e 4 0 ]
"19 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\ftsub.c
[v ___ftsub __ftsub `(f  1 e 4 0 ]
"10 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\sprcadd.c
[v ___fladd __fladd `(d  1 e 4 0 ]
"245
[v ___flsub __flsub `(d  1 e 4 0 ]
"11 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\sprcdiv.c
[v ___fldiv __fldiv `(d  1 e 4 0 ]
"8 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\sprcmul.c
[v ___flmul __flmul `(d  1 e 4 0 ]
"15 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\Umul32.c
[v ___lmul __lmul `(ul  1 e 4 0 ]
"91 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\sources\c99\common\Umul64.c
[v ___omul __omul `(uo  1 e 8 0 ]
"80 C:\Misc\Arm2\TicStepPathMode.X\main.c
[v _get_cmd get_cmd `(v  1 e 1 0 ]
"181
[v _process_cmd process_cmd `(v  1 e 1 0 ]
"288
[v _send_status send_status `(v  1 e 1 0 ]
"343
[v _main main `(v  1 e 1 0 ]
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/dac.c
[v _DAC_Initialize DAC_Initialize `(v  1 e 1 0 ]
"66
[v _DAC_SetOutput DAC_SetOutput `(v  1 e 1 0 ]
[v i2_DAC_SetOutput DAC_SetOutput `(v  1 e 1 0 ]
"56 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/eusart1.c
[v _EUSART1_Initialize EUSART1_Initialize `(v  1 e 1 0 ]
"83
[v _EUSART1_is_rx_ready EUSART1_is_rx_ready `(a  1 e 1 0 ]
"93
[v _EUSART1_Read EUSART1_Read `(uc  1 e 1 0 ]
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/fvr.c
[v _FVR_Initialize FVR_Initialize `(v  1 e 1 0 ]
"52 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/interrupt_manager.c
[v _INTERRUPT_Initialize INTERRUPT_Initialize `(v  1 e 1 0 ]
"58
[v _INTERRUPT_InterruptManager INTERRUPT_InterruptManager `IIH(v  1 e 1 0 ]
"50 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/mcc.c
[v _SYSTEM_Initialize SYSTEM_Initialize `(v  1 e 1 0 ]
"63
[v _OSCILLATOR_Initialize OSCILLATOR_Initialize `(v  1 e 1 0 ]
"59 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/memory.c
[v _FLASH_ReadByte FLASH_ReadByte `(uc  1 e 1 0 ]
"94
[v _FLASH_WriteBlock FLASH_WriteBlock `(c  1 e 1 0 ]
"143
[v _FLASH_EraseBlock FLASH_EraseBlock `(v  1 e 1 0 ]
"166
[v _DATAEE_WriteByte DATAEE_WriteByte `(v  1 e 1 0 ]
"188
[v _DATAEE_ReadByte DATAEE_ReadByte `(uc  1 e 1 0 ]
"57 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/pin_manager.c
[v _PIN_MANAGER_Initialize PIN_MANAGER_Initialize `(v  1 e 1 0 ]
"80 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v _TMR0_Initialize TMR0_Initialize `(v  1 e 1 0 ]
"110
[v _TMR0_StartTimer TMR0_StartTimer `(v  1 e 1 0 ]
"116
[v _TMR0_StopTimer TMR0_StopTimer `(v  1 e 1 0 ]
[v i2_TMR0_StopTimer TMR0_StopTimer `(v  1 e 1 0 ]
"151
[v _TMR0_ISR TMR0_ISR `(v  1 e 1 0 ]
"196
[v _TMR0_SetInterruptHandler TMR0_SetInterruptHandler `(v  1 e 1 0 ]
"200
[v _TMR0_DefaultInterruptHandler TMR0_DefaultInterruptHandler `(v  1 e 1 0 ]
"67 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _TMR1_Initialize TMR1_Initialize `(v  1 e 1 0 ]
"102
[v _TMR1_StopTimer TMR1_StopTimer `(v  1 e 1 0 ]
[v i2_TMR1_StopTimer TMR1_StopTimer `(v  1 e 1 0 ]
"124
[v _TMR1_WriteTimer TMR1_WriteTimer `(v  1 e 1 0 ]
"161
[v _TMR1_ISR_Guts TMR1_ISR_Guts `(v  1 e 1 0 ]
"188
[v _TMR1_ISR TMR1_ISR `(v  1 e 1 0 ]
"222
[v _TMR1_SetInterruptHandler TMR1_SetInterruptHandler `(v  1 e 1 0 ]
"226
[v _TMR1_DefaultInterruptHandler TMR1_DefaultInterruptHandler `(v  1 e 1 0 ]
"232 C:\Program Files (x86)\Microchip\xc8\v2.00\pic\include\pic18f25k50.h
[v _ANSELA ANSELA `VEuc  1 e 1 @3931 ]
"277
[v _ANSELB ANSELB `VEuc  1 e 1 @3932 ]
"327
[v _ANSELC ANSELC `VEuc  1 e 1 @3933 ]
"2458
[v _VREFCON2 VREFCON2 `VEuc  1 e 1 @3963 ]
"2510
[v _VREFCON1 VREFCON1 `VEuc  1 e 1 @3964 ]
"2571
[v _VREFCON0 VREFCON0 `VEuc  1 e 1 @3965 ]
[s S123 . 1 `uc 1 . 1 0 :2:0 
`uc 1 TSRNG 1 0 :1:2 
`uc 1 TSEN 1 0 :1:3 
`uc 1 FVRS 1 0 :2:4 
`uc 1 FVRST 1 0 :1:6 
`uc 1 FVREN 1 0 :1:7 
]
"2591
[s S130 . 1 `uc 1 . 1 0 :4:0 
`uc 1 FVRS0 1 0 :1:4 
`uc 1 FVRS1 1 0 :1:5 
]
[u S134 . 1 `S123 1 . 1 0 `S130 1 . 1 0 ]
[v _VREFCON0bits VREFCON0bits `VES134  1 e 1 @3965 ]
[s S1464 . 1 `uc 1 RB0 1 0 :1:0 
`uc 1 RB1 1 0 :1:1 
`uc 1 RB2 1 0 :1:2 
`uc 1 RB3 1 0 :1:3 
`uc 1 RB4 1 0 :1:4 
`uc 1 RB5 1 0 :1:5 
`uc 1 RB6 1 0 :1:6 
`uc 1 RB7 1 0 :1:7 
]
"2977
[s S1473 . 1 `uc 1 INT0 1 0 :1:0 
`uc 1 INT1 1 0 :1:1 
`uc 1 INT2 1 0 :1:2 
`uc 1 . 1 0 :2:3 
`uc 1 PGM 1 0 :1:5 
`uc 1 PGC 1 0 :1:6 
`uc 1 PGD 1 0 :1:7 
]
[s S1481 . 1 `uc 1 . 1 0 :3:0 
`uc 1 CCP2_PA2 1 0 :1:3 
]
[u S1484 . 1 `S1464 1 . 1 0 `S1473 1 . 1 0 `S1481 1 . 1 0 ]
[v _PORTBbits PORTBbits `VES1484  1 e 1 @3969 ]
"3238
[v _WPUB WPUB `VEuc  1 e 1 @3973 ]
"3472
[v _LATA LATA `VEuc  1 e 1 @3977 ]
[s S1365 . 1 `uc 1 LATA0 1 0 :1:0 
`uc 1 LATA1 1 0 :1:1 
`uc 1 LATA2 1 0 :1:2 
`uc 1 LATA3 1 0 :1:3 
`uc 1 LATA4 1 0 :1:4 
`uc 1 LATA5 1 0 :1:5 
`uc 1 LATA6 1 0 :1:6 
`uc 1 LATA7 1 0 :1:7 
]
"3499
[s S1374 . 1 `uc 1 LA0 1 0 :1:0 
`uc 1 LA1 1 0 :1:1 
`uc 1 LA2 1 0 :1:2 
`uc 1 LA3 1 0 :1:3 
`uc 1 LA4 1 0 :1:4 
`uc 1 LA5 1 0 :1:5 
`uc 1 LA6 1 0 :1:6 
`uc 1 LA7 1 0 :1:7 
]
[u S1383 . 1 `S1365 1 . 1 0 `S1374 1 . 1 0 ]
[v _LATAbits LATAbits `VES1383  1 e 1 @3977 ]
"3584
[v _LATB LATB `VEuc  1 e 1 @3978 ]
[s S471 . 1 `uc 1 LATB0 1 0 :1:0 
`uc 1 LATB1 1 0 :1:1 
`uc 1 LATB2 1 0 :1:2 
`uc 1 LATB3 1 0 :1:3 
`uc 1 LATB4 1 0 :1:4 
`uc 1 LATB5 1 0 :1:5 
`uc 1 LATB6 1 0 :1:6 
`uc 1 LATB7 1 0 :1:7 
]
"3611
[s S480 . 1 `uc 1 LB0 1 0 :1:0 
`uc 1 LB1 1 0 :1:1 
`uc 1 LB2 1 0 :1:2 
`uc 1 LB3 1 0 :1:3 
`uc 1 LB4 1 0 :1:4 
`uc 1 LB5 1 0 :1:5 
`uc 1 LB6 1 0 :1:6 
`uc 1 LB7 1 0 :1:7 
]
[u S489 . 1 `S471 1 . 1 0 `S480 1 . 1 0 ]
[v _LATBbits LATBbits `VES489  1 e 1 @3978 ]
"3696
[v _LATC LATC `VEuc  1 e 1 @3979 ]
[s S1006 . 1 `uc 1 LATC0 1 0 :1:0 
`uc 1 LATC1 1 0 :1:1 
`uc 1 LATC2 1 0 :1:2 
`uc 1 . 1 0 :1:3 
`uc 1 LATC4 1 0 :1:4 
`uc 1 LATC5 1 0 :1:5 
`uc 1 LATC6 1 0 :1:6 
`uc 1 LATC7 1 0 :1:7 
]
"3723
[s S1015 . 1 `uc 1 LC0 1 0 :1:0 
`uc 1 LC1 1 0 :1:1 
`uc 1 LC2 1 0 :1:2 
`uc 1 . 1 0 :1:3 
`uc 1 LC4 1 0 :1:4 
`uc 1 LC5 1 0 :1:5 
`uc 1 LC6 1 0 :1:6 
`uc 1 LC7 1 0 :1:7 
]
[u S1024 . 1 `S1006 1 . 1 0 `S1015 1 . 1 0 ]
[v _LATCbits LATCbits `VES1024  1 e 1 @3979 ]
"4155
[v _TRISA TRISA `VEuc  1 e 1 @3986 ]
"4377
[v _TRISB TRISB `VEuc  1 e 1 @3987 ]
"4599
[v _TRISC TRISC `VEuc  1 e 1 @3988 ]
[s S1310 . 1 `uc 1 TRISC0 1 0 :1:0 
`uc 1 TRISC1 1 0 :1:1 
`uc 1 TRISC2 1 0 :1:2 
`uc 1 . 1 0 :1:3 
`uc 1 TRISC4 1 0 :1:4 
`uc 1 TRISC5 1 0 :1:5 
`uc 1 TRISC6 1 0 :1:6 
`uc 1 TRISC7 1 0 :1:7 
]
"4629
[s S1319 . 1 `uc 1 RC0 1 0 :1:0 
`uc 1 RC1 1 0 :1:1 
`uc 1 RC2 1 0 :1:2 
`uc 1 . 1 0 :3:3 
`uc 1 RC6 1 0 :1:6 
`uc 1 RC7 1 0 :1:7 
]
[u S1326 . 1 `S1310 1 . 1 0 `S1319 1 . 1 0 ]
[v _TRISCbits TRISCbits `VES1326  1 e 1 @3988 ]
"5241
[v _OSCTUNE OSCTUNE `VEuc  1 e 1 @3995 ]
[s S726 . 1 `uc 1 TMR1IE 1 0 :1:0 
`uc 1 TMR2IE 1 0 :1:1 
`uc 1 CCP1IE 1 0 :1:2 
`uc 1 SSPIE 1 0 :1:3 
`uc 1 TXIE 1 0 :1:4 
`uc 1 RCIE 1 0 :1:5 
`uc 1 ADIE 1 0 :1:6 
`uc 1 ACTIE 1 0 :1:7 
]
"5410
[s S735 . 1 `uc 1 . 1 0 :3:0 
`uc 1 SSP1IE 1 0 :1:3 
`uc 1 TX1IE 1 0 :1:4 
`uc 1 RC1IE 1 0 :1:5 
`uc 1 . 1 0 :1:6 
`uc 1 STIE 1 0 :1:7 
]
[s S742 . 1 `uc 1 . 1 0 :7:0 
`uc 1 PSPIE 1 0 :1:7 
]
[u S745 . 1 `S726 1 . 1 0 `S735 1 . 1 0 `S742 1 . 1 0 ]
[v _PIE1bits PIE1bits `VES745  1 e 1 @3997 ]
[s S168 . 1 `uc 1 TMR1IF 1 0 :1:0 
`uc 1 TMR2IF 1 0 :1:1 
`uc 1 CCP1IF 1 0 :1:2 
`uc 1 SSPIF 1 0 :1:3 
`uc 1 TXIF 1 0 :1:4 
`uc 1 RCIF 1 0 :1:5 
`uc 1 ADIF 1 0 :1:6 
`uc 1 ACTIF 1 0 :1:7 
]
"5509
[s S177 . 1 `uc 1 . 1 0 :3:0 
`uc 1 SSP1IF 1 0 :1:3 
`uc 1 TX1IF 1 0 :1:4 
`uc 1 RC1IF 1 0 :1:5 
`uc 1 . 1 0 :1:6 
`uc 1 STIF 1 0 :1:7 
]
[s S184 . 1 `uc 1 . 1 0 :7:0 
`uc 1 PSPIF 1 0 :1:7 
]
[u S187 . 1 `S168 1 . 1 0 `S177 1 . 1 0 `S184 1 . 1 0 ]
[v _PIR1bits PIR1bits `VES187  1 e 1 @3998 ]
[s S1174 . 1 `uc 1 CCP2IF 1 0 :1:0 
`uc 1 TMR3IF 1 0 :1:1 
`uc 1 HLVDIF 1 0 :1:2 
`uc 1 BCLIF 1 0 :1:3 
`uc 1 EEIF 1 0 :1:4 
`uc 1 C2IF 1 0 :1:5 
`uc 1 C1IF 1 0 :1:6 
`uc 1 OSCFIF 1 0 :1:7 
]
"5806
[s S1183 . 1 `uc 1 . 1 0 :2:0 
`uc 1 LVDIF 1 0 :1:2 
`uc 1 BCL1IF 1 0 :1:3 
`uc 1 . 1 0 :1:4 
`uc 1 CM2IF 1 0 :1:5 
`uc 1 CM1IF 1 0 :1:6 
]
[s S1190 . 1 `uc 1 . 1 0 :6:0 
`uc 1 CMIF 1 0 :1:6 
]
[u S1193 . 1 `S1174 1 . 1 0 `S1183 1 . 1 0 `S1190 1 . 1 0 ]
[v _PIR2bits PIR2bits `VES1193  1 e 1 @4001 ]
[s S1139 . 1 `uc 1 RD 1 0 :1:0 
`uc 1 WR 1 0 :1:1 
`uc 1 WREN 1 0 :1:2 
`uc 1 WRERR 1 0 :1:3 
`uc 1 FREE 1 0 :1:4 
`uc 1 . 1 0 :1:5 
`uc 1 CFGS 1 0 :1:6 
`uc 1 EEPGD 1 0 :1:7 
]
"6163
[s S1148 . 1 `uc 1 . 1 0 :6:0 
`uc 1 EEFS 1 0 :1:6 
]
[u S1151 . 1 `S1139 1 . 1 0 `S1148 1 . 1 0 ]
[v _EECON1bits EECON1bits `VES1151  1 e 1 @4006 ]
"6208
[v _EECON2 EECON2 `VEuc  1 e 1 @4007 ]
"6228
[v _EEDATA EEDATA `VEuc  1 e 1 @4008 ]
"6235
[v _EEADR EEADR `VEuc  1 e 1 @4009 ]
"6242
[v _RCSTA1 RCSTA1 `VEuc  1 e 1 @4011 ]
[s S295 . 1 `uc 1 RX9D 1 0 :1:0 
`uc 1 OERR 1 0 :1:1 
`uc 1 FERR 1 0 :1:2 
`uc 1 ADDEN 1 0 :1:3 
`uc 1 CREN 1 0 :1:4 
`uc 1 SREN 1 0 :1:5 
`uc 1 RX9 1 0 :1:6 
`uc 1 SPEN 1 0 :1:7 
]
"6281
[s S304 . 1 `uc 1 . 1 0 :3:0 
`uc 1 ADEN 1 0 :1:3 
]
[s S307 . 1 `uc 1 RCD8 1 0 :1:0 
`uc 1 . 1 0 :5:1 
`uc 1 RC8_9 1 0 :1:6 
]
[s S311 . 1 `uc 1 . 1 0 :6:0 
`uc 1 RC9 1 0 :1:6 
]
[s S314 . 1 `uc 1 . 1 0 :5:0 
`uc 1 SRENA 1 0 :1:5 
]
[u S317 . 1 `S295 1 . 1 0 `S304 1 . 1 0 `S307 1 . 1 0 `S311 1 . 1 0 `S314 1 . 1 0 ]
[v _RCSTA1bits RCSTA1bits `VES317  1 e 1 @4011 ]
"6448
[v _TXSTA1 TXSTA1 `VEuc  1 e 1 @4012 ]
[s S211 . 1 `uc 1 TX9D 1 0 :1:0 
`uc 1 TRMT 1 0 :1:1 
`uc 1 BRGH 1 0 :1:2 
`uc 1 SENDB 1 0 :1:3 
`uc 1 SYNC 1 0 :1:4 
`uc 1 TXEN 1 0 :1:5 
`uc 1 TX9 1 0 :1:6 
`uc 1 CSRC 1 0 :1:7 
]
"6506
[s S220 . 1 `uc 1 TXD8 1 0 :1:0 
`uc 1 . 1 0 :5:1 
`uc 1 TX8_9 1 0 :1:6 
]
[s S224 . 1 `uc 1 . 1 0 :2:0 
`uc 1 BRGH1 1 0 :1:2 
]
[s S227 . 1 `uc 1 . 1 0 :7:0 
`uc 1 CSRC1 1 0 :1:7 
]
[s S230 . 1 `uc 1 . 1 0 :3:0 
`uc 1 SENDB1 1 0 :1:3 
]
[s S233 . 1 `uc 1 . 1 0 :4:0 
`uc 1 SYNC1 1 0 :1:4 
]
[s S236 . 1 `uc 1 . 1 0 :1:0 
`uc 1 TRMT1 1 0 :1:1 
]
[s S239 . 1 `uc 1 . 1 0 :6:0 
`uc 1 TX91 1 0 :1:6 
]
[s S242 . 1 `uc 1 TX9D1 1 0 :1:0 
]
[s S244 . 1 `uc 1 . 1 0 :5:0 
`uc 1 TXEN1 1 0 :1:5 
]
[u S247 . 1 `S211 1 . 1 0 `S220 1 . 1 0 `S224 1 . 1 0 `S227 1 . 1 0 `S230 1 . 1 0 `S233 1 . 1 0 `S236 1 . 1 0 `S239 1 . 1 0 `S242 1 . 1 0 `S244 1 . 1 0 ]
[v _TXSTA1bits TXSTA1bits `VES247  1 e 1 @4012 ]
"6742
[v _TXREG1 TXREG1 `VEuc  1 e 1 @4013 ]
"6780
[v _RCREG1 RCREG1 `VEuc  1 e 1 @4014 ]
"6818
[v _SPBRG1 SPBRG1 `VEuc  1 e 1 @4015 ]
"6956
[v _SPBRGH1 SPBRGH1 `VEuc  1 e 1 @4016 ]
"7401
[v _ACTCON ACTCON `VEuc  1 e 1 @4021 ]
"7891
[v _BAUDCON1 BAUDCON1 `VEuc  1 e 1 @4024 ]
"11017
[v _T1GCON T1GCON `VEuc  1 e 1 @4044 ]
[s S934 . 1 `uc 1 . 1 0 :3:0 
`uc 1 T1GGO_NOT_T1DONE 1 0 :1:3 
]
"11063
[s S937 . 1 `uc 1 T1GSS 1 0 :2:0 
`uc 1 T1GVAL 1 0 :1:2 
`uc 1 T1GGO_nT1DONE 1 0 :1:3 
`uc 1 T1GSPM 1 0 :1:4 
`uc 1 T1GTM 1 0 :1:5 
`uc 1 T1GPOL 1 0 :1:6 
`uc 1 TMR1GE 1 0 :1:7 
]
[s S945 . 1 `uc 1 T1GSS0 1 0 :1:0 
`uc 1 T1GSS1 1 0 :1:1 
`uc 1 . 1 0 :1:2 
`uc 1 T1GGO 1 0 :1:3 
]
[s S950 . 1 `uc 1 . 1 0 :3:0 
`uc 1 NOT_T1DONE 1 0 :1:3 
]
[s S953 . 1 `uc 1 . 1 0 :3:0 
`uc 1 nT1DONE 1 0 :1:3 
]
[s S956 . 1 `uc 1 . 1 0 :3:0 
`uc 1 T1DONE 1 0 :1:3 
]
[s S959 . 1 `uc 1 . 1 0 :3:0 
`uc 1 T1GGO_NOT_DONE 1 0 :1:3 
]
[s S962 . 1 `uc 1 . 1 0 :3:0 
`uc 1 T1GGO_nDONE 1 0 :1:3 
]
[u S965 . 1 `S934 1 . 1 0 `S937 1 . 1 0 `S945 1 . 1 0 `S950 1 . 1 0 `S953 1 . 1 0 `S956 1 . 1 0 `S959 1 . 1 0 `S962 1 . 1 0 ]
[v _T1GCONbits T1GCONbits `VES965  1 e 1 @4044 ]
"11148
[v _T1CON T1CON `VEuc  1 e 1 @4045 ]
[s S513 . 1 `uc 1 . 1 0 :2:0 
`uc 1 NOT_T1SYNC 1 0 :1:2 
]
"11187
[s S516 . 1 `uc 1 TMR1ON 1 0 :1:0 
`uc 1 RD16 1 0 :1:1 
`uc 1 nT1SYNC 1 0 :1:2 
`uc 1 SOSCEN 1 0 :1:3 
`uc 1 T1CKPS 1 0 :2:4 
`uc 1 TMR1CS 1 0 :2:6 
]
[s S523 . 1 `uc 1 . 1 0 :1:0 
`uc 1 T1RD16 1 0 :1:1 
`uc 1 T1SYNC 1 0 :1:2 
`uc 1 T1SOSCEN 1 0 :1:3 
`uc 1 T1CKPS0 1 0 :1:4 
`uc 1 T1CKPS1 1 0 :1:5 
`uc 1 TMR1CS0 1 0 :1:6 
`uc 1 TMR1CS1 1 0 :1:7 
]
[s S532 . 1 `uc 1 . 1 0 :3:0 
`uc 1 T1OSCEN 1 0 :1:3 
]
[s S535 . 1 `uc 1 . 1 0 :3:0 
`uc 1 SOSCEN1 1 0 :1:3 
`uc 1 . 1 0 :3:4 
`uc 1 RD161 1 0 :1:7 
]
[u S540 . 1 `S513 1 . 1 0 `S516 1 . 1 0 `S523 1 . 1 0 `S532 1 . 1 0 `S535 1 . 1 0 ]
[v _T1CONbits T1CONbits `VES540  1 e 1 @4045 ]
"11277
[v _TMR1 TMR1 `VEus  1 e 2 @4046 ]
"11284
[v _TMR1L TMR1L `VEuc  1 e 1 @4046 ]
"11304
[v _TMR1H TMR1H `VEuc  1 e 1 @4047 ]
[s S631 . 1 `uc 1 NOT_BOR 1 0 :1:0 
]
"11367
[s S633 . 1 `uc 1 . 1 0 :1:0 
`uc 1 NOT_POR 1 0 :1:1 
]
[s S636 . 1 `uc 1 . 1 0 :2:0 
`uc 1 NOT_PD 1 0 :1:2 
]
[s S639 . 1 `uc 1 . 1 0 :3:0 
`uc 1 NOT_TO 1 0 :1:3 
]
[s S642 . 1 `uc 1 . 1 0 :4:0 
`uc 1 NOT_RI 1 0 :1:4 
]
[s S645 . 1 `uc 1 nBOR 1 0 :1:0 
`uc 1 nPOR 1 0 :1:1 
`uc 1 nPD 1 0 :1:2 
`uc 1 nTO 1 0 :1:3 
`uc 1 nRI 1 0 :1:4 
`uc 1 . 1 0 :1:5 
`uc 1 SBOREN 1 0 :1:6 
`uc 1 IPEN 1 0 :1:7 
]
[s S654 . 1 `uc 1 BOR 1 0 :1:0 
`uc 1 POR 1 0 :1:1 
`uc 1 PD 1 0 :1:2 
`uc 1 TO 1 0 :1:3 
`uc 1 RI 1 0 :1:4 
]
[u S660 . 1 `S631 1 . 1 0 `S633 1 . 1 0 `S636 1 . 1 0 `S639 1 . 1 0 `S642 1 . 1 0 `S645 1 . 1 0 `S654 1 . 1 0 ]
[v _RCONbits RCONbits `VES660  1 e 1 @4048 ]
"11485
[v _OSCCON2 OSCCON2 `VEuc  1 e 1 @4050 ]
"11547
[v _OSCCON OSCCON `VEuc  1 e 1 @4051 ]
"11630
[v _T0CON T0CON `VEuc  1 e 1 @4053 ]
[s S379 . 1 `uc 1 T0PS 1 0 :3:0 
`uc 1 PSA 1 0 :1:3 
`uc 1 T0SE 1 0 :1:4 
`uc 1 T0CS 1 0 :1:5 
`uc 1 T08BIT 1 0 :1:6 
`uc 1 TMR0ON 1 0 :1:7 
]
"11650
[s S386 . 1 `uc 1 T0PS0 1 0 :1:0 
`uc 1 T0PS1 1 0 :1:1 
`uc 1 T0PS2 1 0 :1:2 
]
[u S390 . 1 `S379 1 . 1 0 `S386 1 . 1 0 ]
[v _T0CONbits T0CONbits `VES390  1 e 1 @4053 ]
"11707
[v _TMR0L TMR0L `VEuc  1 e 1 @4054 ]
"11727
[v _TMR0H TMR0H `VEuc  1 e 1 @4055 ]
[s S73 . 1 `uc 1 . 1 0 :7:0 
`uc 1 NOT_RBPU 1 0 :1:7 
]
"12366
[s S76 . 1 `uc 1 IOCIP 1 0 :1:0 
`uc 1 . 1 0 :1:1 
`uc 1 TMR0IP 1 0 :1:2 
`uc 1 . 1 0 :1:3 
`uc 1 INTEDG2 1 0 :1:4 
`uc 1 INTEDG1 1 0 :1:5 
`uc 1 INTEDG0 1 0 :1:6 
`uc 1 nRBPU 1 0 :1:7 
]
[s S85 . 1 `uc 1 . 1 0 :2:0 
`uc 1 T0IP 1 0 :1:2 
`uc 1 . 1 0 :4:3 
`uc 1 RBPU 1 0 :1:7 
]
[u S90 . 1 `S73 1 . 1 0 `S76 1 . 1 0 `S85 1 . 1 0 ]
[v _INTCON2bits INTCON2bits `VES90  1 e 1 @4081 ]
[s S407 . 1 `uc 1 IOCIF 1 0 :1:0 
`uc 1 INT0IF 1 0 :1:1 
`uc 1 TMR0IF 1 0 :1:2 
`uc 1 IOCIE 1 0 :1:3 
`uc 1 INT0IE 1 0 :1:4 
`uc 1 TMR0IE 1 0 :1:5 
`uc 1 PEIE_GIEL 1 0 :1:6 
`uc 1 GIE_GIEH 1 0 :1:7 
]
"12448
[s S416 . 1 `uc 1 . 1 0 :1:0 
`uc 1 INT0F 1 0 :1:1 
`uc 1 T0IF 1 0 :1:2 
`uc 1 . 1 0 :1:3 
`uc 1 INT0E 1 0 :1:4 
`uc 1 T0IE 1 0 :1:5 
`uc 1 PEIE 1 0 :1:6 
`uc 1 GIE 1 0 :1:7 
]
[s S425 . 1 `uc 1 . 1 0 :6:0 
`uc 1 GIEL 1 0 :1:6 
`uc 1 GIEH 1 0 :1:7 
]
[u S429 . 1 `S407 1 . 1 0 `S416 1 . 1 0 `S425 1 . 1 0 ]
[v _INTCONbits INTCONbits `VES429  1 e 1 @4082 ]
"12580
[v _TABLAT TABLAT `VEuc  1 e 1 @4085 ]
"12609
[v _TBLPTRL TBLPTRL `VEuc  1 e 1 @4086 ]
"12629
[v _TBLPTRH TBLPTRH `VEuc  1 e 1 @4087 ]
"12649
[v _TBLPTRU TBLPTRU `VEuc  1 e 1 @4088 ]
"14653
[v _PLLRDY PLLRDY `VEb  1 e 0 @32407 ]
"57 C:\Misc\Arm2\TicStepPathMode.X\main.c
[v _cmd_buf cmd_buf `[20]uc  1 e 20 0 ]
"65
[v _rcv_state rcv_state `uc  1 e 1 0 ]
"71
[v _send_state send_state `uc  1 e 1 0 ]
"73
[v _datacount datacount `uc  1 e 1 0 ]
[v _numdat numdat `uc  1 e 1 0 ]
"74
[v _my_address my_address `uc  1 e 1 0 ]
[v _my_group_address my_group_address `uc  1 e 1 0 ]
[v _group_leader group_leader `uc  1 e 1 0 ]
"75
[v _cksum_err cksum_err `a  1 e 1 0 ]
"76
[v _cksum_calc cksum_calc `uc  1 e 1 0 ]
"77
[v _hold_current hold_current `uc  1 e 1 0 ]
[v _run_current run_current `uc  1 e 1 0 ]
"61 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v _TMR0_InterruptHandler TMR0_InterruptHandler `*.37(v  1 e 2 0 ]
"63
[v _timer0ReloadVal timer0ReloadVal `VEus  1 e 2 0 ]
"65
[v _PathBuffer PathBuffer `VE[127]us  1 e 254 0 ]
"66
[v _PathHead PathHead `VEuc  1 e 1 0 ]
"67
[v _PathTail PathTail `VEuc  1 e 1 0 ]
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _timer1ReloadVal timer1ReloadVal `VEus  1 e 2 0 ]
"59
[v _PositionCounter PositionCounter `VEl  1 e 4 0 ]
"60
[v _TMR1_InterruptHandler TMR1_InterruptHandler `*.37(v  1 e 2 0 ]
"61
[v _dirbit dirbit `VEa  1 e 1 0 ]
"343 C:\Misc\Arm2\TicStepPathMode.X\main.c
[v _main main `(v  1 e 1 0 ]
{
"404
} 0
"288
[v _send_status send_status `(v  1 e 1 0 ]
{
"290
[v send_status@statbyte statbyte `uc  1 a 1 7 ]
"337
} 0
"181
[v _process_cmd process_cmd `(v  1 e 1 0 ]
{
"184
[v process_cmd@mem_addr mem_addr `us  1 a 2 13 ]
"183
[v process_cmd@i i `uc  1 a 1 18 ]
[v process_cmd@ndata ndata `uc  1 a 1 17 ]
[v process_cmd@temp_cur temp_cur `uc  1 a 1 16 ]
[v process_cmd@command command `uc  1 a 1 15 ]
"282
} 0
"102 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _TMR1_StopTimer TMR1_StopTimer `(v  1 e 1 0 ]
{
"106
} 0
"116 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v _TMR0_StopTimer TMR0_StopTimer `(v  1 e 1 0 ]
{
"120
} 0
"110
[v _TMR0_StartTimer TMR0_StartTimer `(v  1 e 1 0 ]
{
"114
} 0
"166 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/memory.c
[v _DATAEE_WriteByte DATAEE_WriteByte `(v  1 e 1 0 ]
{
[v DATAEE_WriteByte@bAdd bAdd `uc  1 a 1 wreg ]
"168
[v DATAEE_WriteByte@GIEBitValue GIEBitValue `uc  1 a 1 7 ]
"166
[v DATAEE_WriteByte@bAdd bAdd `uc  1 a 1 wreg ]
[v DATAEE_WriteByte@bData bData `uc  1 p 1 5 ]
"168
[v DATAEE_WriteByte@bAdd bAdd `uc  1 a 1 6 ]
"186
} 0
"66 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/dac.c
[v _DAC_SetOutput DAC_SetOutput `(v  1 e 1 0 ]
{
[v DAC_SetOutput@inputData inputData `uc  1 a 1 wreg ]
[v DAC_SetOutput@inputData inputData `uc  1 a 1 wreg ]
"68
[v DAC_SetOutput@inputData inputData `uc  1 a 1 5 ]
"69
} 0
"80 C:\Misc\Arm2\TicStepPathMode.X\main.c
[v _get_cmd get_cmd `(v  1 e 1 0 ]
{
"129
} 0
"83 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/eusart1.c
[v _EUSART1_is_rx_ready EUSART1_is_rx_ready `(a  1 e 1 0 ]
{
"86
} 0
"93
[v _EUSART1_Read EUSART1_Read `(uc  1 e 1 0 ]
{
"109
} 0
"50 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/mcc.c
[v _SYSTEM_Initialize SYSTEM_Initialize `(v  1 e 1 0 ]
{
"61
} 0
"67 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _TMR1_Initialize TMR1_Initialize `(v  1 e 1 0 ]
{
"94
} 0
"222
[v _TMR1_SetInterruptHandler TMR1_SetInterruptHandler `(v  1 e 1 0 ]
{
[v TMR1_SetInterruptHandler@InterruptHandler InterruptHandler `*.37(v  1 p 2 5 ]
"224
} 0
"80 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v _TMR0_Initialize TMR0_Initialize `(v  1 e 1 0 ]
{
"108
} 0
"196
[v _TMR0_SetInterruptHandler TMR0_SetInterruptHandler `(v  1 e 1 0 ]
{
[v TMR0_SetInterruptHandler@InterruptHandler InterruptHandler `*.37(v  1 p 2 5 ]
"198
} 0
"57 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/pin_manager.c
[v _PIN_MANAGER_Initialize PIN_MANAGER_Initialize `(v  1 e 1 0 ]
{
"94
} 0
"63 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/mcc.c
[v _OSCILLATOR_Initialize OSCILLATOR_Initialize `(v  1 e 1 0 ]
{
"77
} 0
"52 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/interrupt_manager.c
[v _INTERRUPT_Initialize INTERRUPT_Initialize `(v  1 e 1 0 ]
{
"56
} 0
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/fvr.c
[v _FVR_Initialize FVR_Initialize `(v  1 e 1 0 ]
{
"62
} 0
"56 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/eusart1.c
[v _EUSART1_Initialize EUSART1_Initialize `(v  1 e 1 0 ]
{
"76
} 0
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/dac.c
[v _DAC_Initialize DAC_Initialize `(v  1 e 1 0 ]
{
"64
} 0
"188 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/memory.c
[v _DATAEE_ReadByte DATAEE_ReadByte `(uc  1 e 1 0 ]
{
[v DATAEE_ReadByte@bAdd bAdd `uc  1 a 1 wreg ]
[v DATAEE_ReadByte@bAdd bAdd `uc  1 a 1 wreg ]
"190
[v DATAEE_ReadByte@bAdd bAdd `uc  1 a 1 5 ]
"198
} 0
"58 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/interrupt_manager.c
[v _INTERRUPT_InterruptManager INTERRUPT_InterruptManager `IIH(v  1 e 1 0 ]
{
"80
} 0
"188 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _TMR1_ISR TMR1_ISR `(v  1 e 1 0 ]
{
"219
} 0
"151 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v _TMR0_ISR TMR0_ISR `(v  1 e 1 0 ]
{
"193
} 0
"102 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v i2_TMR1_StopTimer TMR1_StopTimer `(v  1 e 1 0 ]
{
"106
} 0
"116 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr0.c
[v i2_TMR0_StopTimer TMR0_StopTimer `(v  1 e 1 0 ]
{
"120
} 0
"66 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/dac.c
[v i2_DAC_SetOutput DAC_SetOutput `(v  1 e 1 0 ]
{
[v i2DAC_SetOutput@inputData inputData `uc  1 a 1 wreg ]
[v i2DAC_SetOutput@inputData inputData `uc  1 a 1 wreg ]
"68
[v i2DAC_SetOutput@inputData inputData `uc  1 a 1 0 ]
"69
} 0
"161 C:\Misc\Arm2\TicStepPathMode.X\mcc_generated_files/tmr1.c
[v _TMR1_ISR_Guts TMR1_ISR_Guts `(v  1 e 1 0 ]
{
"186
} 0